In 1965, Dr. Gordon Moore, then Director of Research and Development for Fairchild Semiconductor, made the observation that the number of transistor devices per integrated circuit had been doubling every couple of years since the creation of the first integrated circuits in the late 1950's and that he expected the trend to continue for the foreseeable future. This observation was dubbed “Moore's Law” by the trade press. Now almost 40 years later, despite numerous dire predictions of fundamental obstacles, unrelenting industry efforts towards every-increasing semiconductor density have effectively affirmed Dr. Moore's prophetic observation, and the trend is still expected to continue unabated for the foreseeable future. The process of reducing semiconductor device size to increase integrated circuit density is generally referred to as “scaling”.
Ongoing scaling efforts of semiconductor MOS (Metal-Oxide-Semiconductor) devices not only contribute to higher integrated circuit packing density, but also improve integrated circuit performance. As the scaling process proceeds towards the physical limits of currently available MOS technologies and techniques, new technologies and techniques are developed to further decrease device size and increase device performance. As MOS device size decreases, tremendous challenges arise in a variety of areas, including source/drain contact resistance and current carrying capacity. In these two areas at least, extremely small size tends to work against performance.
One approach that has been employed to improve current carrying capacity of extremely small-geometry FETs is the creation of “double gate” (also referred to as dual-gate herein) transistors. In principle, double-gate transistors act something like two transistors in parallel, thereby improving current flow between source and drain. Two major types of double-gate transistors have been demonstrated: the planar double-gate transistor and the double-gate Fin-FET.
The planar double-gate FET is not unlike a conventional single gate transistor in that it has a horizontal “planar” transistor body with a source and drain at each end and a channel therebetween. Unlike single-gate transistors, however, the planar double-gate FET has a second gate below the transistor body effectively creating a second, parallel channel between the source and drain. However, there is considerable process complexity involved in forming the second, buried gate and in connecting to it, and the planar double-gate transistor is not significantly different from conventional planar transistor structures in terms of its ability to be scaled. Such planar devices are rapidly approaching the physical limits of scaling.
The double-gate Fin-FET employs thin vertical silicon “fins” that act as the transistor body. Horizontally opposed ends of the fin act as source and drain. The gate structure is formed around the fin in an inverted “U” configuration such that the fin has parallel gates formed along both vertical sidewalls thereof. As in the planar double-gate transistor, the double-gate Fin-FET improves current flow between source and drain by effectively creating parallel channels therebetween. Current flows horizontally through the fin between source and drain when the double gate is appropriately biased. Because the transistor body of the Fin-FET is a thin vertical structure, there can be considerable space savings over similar planar devices. Series resistance in Fin-FETs is a significant problem, however.